Jeff

1/27/2015
Chandler, AZ

Position Desired

Electronics Engineering
Chandler, AZ; Austin, TX
Yes

Resume

Cell Ph # 480-510-6132

Type of Job

Looking for a job which utilizes my technical skill set, which is in system design and analog design. I know Simulink, Matlab, Spice Simulators and I can code in C language as well a Perl. I can specify and simulate block performance requirements in a larger system. In my latest job I had to work with Xilinx Spartan 6, Simulink and System Generator and am comfortable realizing FPGA systems. I am also comfortable and do an excellent job in project management and have used Microsoft Project.


Professional Preparation

Trine University Angola, IN Electrical Engineering BSEE 1979

Appointments

2013 - Present
Chief Technical Officer of UON Technologies LLC
2012-2013
Quantenna Principal/Staff Analog Design Engineer
2009-2012 Fujitsu FSWP – System Design Engineer
2004-2009
Freescale – System Design Engineer
1982-2004
1979-1982 Motoroal SPS – Analog Design Engineer
Mostek Corporation – Test Engineer

Closely Related Projects
2013 - Present
Chief Technical Officer of UON Technologies LLC, currently designing product base Sensorbots to be released in fall of 2014. In 2013 led the design for Execbots which for a technical demonstration for MacArtney an important UON partner for UON.
2012-2013
Quantenna Principal/Staff Analog Design Engineer, designed a 5th order Chebyshev RX filter for Quantenna’s RF transceiver offering.
2009-2012 Fujitsu FSWP – System Design Engineer
2012-2013, Worked on RF planning, specification for 3Gpp Long Term Evolution (LTE) Carrier Aggregation (CA) planning and release for cellular market.
2011-2012, Simulated in Simulink an all digital RF Tx PLL to be used for Fujitsu’s cell phone’s which would allow instant jump to the desired channel transmission and reception.
2009-2011, Defined the baseband digital Tx, interpolation, Pulse shape digital filters, droop compensation as well as DC offset correction circuit for Fujitsu 2G, 3G and WCDMA transceiver chip.
Documented how the RX IQ digital balancing worked.
2004-2009
Freescale – System Design Engineer
2008-2009, Part of the team which defined the on chip 0.13u Wifi block specification
2004-2009, Designed baseband analog Rx filters for Family Service Radio. Designed the TX Python analog filter
1982-2004 Motoroal SPS – Analog Design Engineer, designed, Sigma-Delta A/D’s, crystal oscillators, references, opamps, DACs and comparators. Designed Motorola’s 1st all CMOS RS232 chip, MC145406


Closely Related Publications
(2010). “A SAW-less CMOS TX for EGPRS and WCDMA” IEEE/Radio Frequency Integrated Circuits Symposium (RFIC)

(2005). “A tri-band (2100/1900/800 MHz) single-chip cellu...

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