EMBEDDED SYSTEMS / FPGA / FIRMWARE / RF / WIRELESS / FILTERING / SIGNAL PROCESSING
Creative, skilled, and results oriented electrical engineer seeking an opportunity to contribute to an organization that shares the same passion for developing cutting-edge technologies utilizing FPGAs and RF & wireless communications.
[Technical Skills]
Hardware Design
* Design: RF and base-band amplifiers, filters (analog and digital), impedance matching, s-parameters, dividers, oscillators, digital logic, micro-controllers, memories, capacitive touch, NFC, battery charge & protection
* CAD tools: Cadence OrCAD, Mentor Graphics PADS, and Advanced Design Systems (ADS)
FPGA Design
* Languages: VHDL (primary) and Verilog
* Altera: Cyclone II, Cyclone IV, Quartus-II
* Xilinx: Spartan-6, Zynq 7010, Xilinx ISE & Vivado Toolchains
Embedded & Software Development
* Languages: C, C++, C#, MATLAB, PERL, Python, TCL, VBScript, JavaScript
* Operating Systems: FreeRTOS, eCos, µC/OS-II, VxWorks, Linux, Windows
* Architectures: ARM Cortex-M3/M4, NIOS-II, 8051, PIC18/24/32
* Protocol & Peripherals: Bluetooth 4.0 Low Energy (BLE), SPI, I2C, UART, DMA, some CAN experience
* Development Tools: Clearcase, SVN, Plastic SCM, Git, IAR EWARM/EW8051, Eclipse, GCC, VIM
* Equipment: Spectrum, Vector Network, Logic, DC Power, and BT Protocol Analyzers, Oscilloscopes, meters
[Selected Experience Profile]
RF Hardware/Software/Systems Engineer (Concurrent Roles) LS Research, LLC Apr. 2013 – Present
* Designed a Wi-Fi controlled light dimmer control board using the Qualcomm AR4100P Wi-Fi SIP and STM32L151RC microcontroller. The board generated control signals for leading & trailing-edge phase cutting of mains to dim up to 1kW of either inductive or capacitive light loads. Tuned a capacitive touch user interface to the enclosure, and integrated it with LEDs feedback. Assisted in designing a secondary board that provided an isolated power supply and diming circuitry.
* Assisted with ICD, power supply design, and schematic capture of a modular software defined radio (SDR).
* Performed NFC consulting to determine optimal placement and tuning of antenna on metal housing. Utilized the PN532 NFC controller and Pulse W3579 ferrite backed antenna to read standard MIFARE 1k cards.
* Primary developer of a re-usable C’99 modular based framework. The framework can be used across multiple RTOS platforms, decreasing design time and providing a common platform for the engineering team.
* Led a co-development effort with customer and third-party companies to design a wearable device with fitness and personal security capabilities. The wearable used a STM32L4 ARM Cortex-M4 µC and the TI CC2640 BLE SoC. Main development tasks included system architecture, communications (inter-process and inter-device), display GUI & drivers, watchdog management, and an inter-device error logging infrastructure.
* Led a co-development effort with customer to design an arrhythmia monitoring system. The system consisted of a BLE wearable device, a BLE-to-Cellular gateway, and remote server. Implemented BLE firmware on the TI CC2541 BLE SoC (8051 core). Development efforts included custom services, serial protocol development, application logic, and driver development. Implemented both BLE Peripheral & Central roles. Created MATLAB simulations to determining the communication intervals and protocol necessary to meet a very tight power budget while having minimum latency and optimal throughput.
* Aided in performing risk assessment, milestone tracking, project effort quotes, and project resource allocation.
* Assisted with process definition, improvement, and roll-out. Translated marketing level requirements to testable engineering level requirements. Authored and executed both hardware and software test plans to verify performance and functional requirements. Acted as project engineer to be the primary technical interface to customers, layout development plans, and coordinate with project management.
Firmware Engineer GE Healthcare: Magnetic Resonance Imaging Oct. 2010 – Apr. 2013
* Discovered, and aided in resolving ECG noise issues within the Rx chain of the Physiological Acquisition Controller. Created an automated test infrastructure and MATLAB scripts to perform spectral analysis. Worked with hardware team to identify non-integer based decimation of samples that manifested as large noise components. All changes identified ultimately reduced the noise floor by more than 20dB.
* Implemented several key features of the Scan Room Interface including flash downloading utility, custom CPLD register interface, and velocity-based motion controller. Most of the development took place utilizing µC/OS-II on a NIOS-II soft-core processor realized within an Altera Cyclone IV FPGA. Some task spanned device boundaries and required development in a PowerPC target utilizing VxWorks.
* Velocity-based motion controller design was used to facilitate patient positioning within 200µm of the target position regardless of patient weight, power supply, or mechanical setup. Developed MATLAB, PERL, and Linux shell scripts to plot positioning distributions for predicting positioning reliability, and gathering data utilized to tune the PID and supervisor control loops. Created an automated test infrastructure and scripts to perform a programmable series of movements used to show positioning repeatability to 5-nines. Mechanically maintained systems proved repeatability to nearly 6-nines.
* Developed a VHDL speed estimator that interfaced NIOS-II firmware. The speed estimator timed state transitions of a quadrature encoder, implemented change of direction detection, and filtering to remove artificial velocity transient artifacts generated by change in direction and encoder noise.
* Developed VHDL test-benches and ...
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